“Although many people are not familiar with DRAM, DRAM is not a novelty. Because, when using a computer, we are all dealing with DRAM. In order to improve everyone’s understanding of DRAM, this article will introduce DRAM based on two points: 1. Introduction to the organization of DRAM, and 2. Introduction to DRAM modules.
Although many people are not familiar with DRAM, DRAM is not a novelty. Because, when using a computer, we are all dealing with DRAM. In order to improve everyone’s understanding of DRAM, this article will introduce DRAM based on two points: 1. Introduction to the organization of DRAM, and 2. Introduction to DRAM modules.
1. Introduction to DRAM Organization
As the system’s demand for memory capacity, bandwidth, and performance increases, the system will access multiple DRAM Devices. Different organization methods of multiple DRAM Devices will bring different effects. This article will briefly introduce the different organizational methods and their effects.
1. Organization of Single Channel DRAM Controller
Single Channel means that the DRAM Controller has only one set of control and data buses. In this scenario, the connection between the DRAM Controller and single or multiple DRAM Devices is as follows:
1.1 Connect a single DRAM Device
Single Channel connecting a single DRAM Device is the most common way of organization. Due to factors such as cost and process, a single DRAM Device is limited in terms of bus width and capacity. In products that require large bandwidth and large capacity, multiple DRAM Devices are usually connected.
1.2 Connecting Multiple DRAM Devices
In the above figure, multiple DRAM Devices share the control and data bus, and the DRAM Controller separately accesses each DRAM Devices through Chip Select time-sharing. In addition, when one of the Devices enters the refresh cycle, the DRAM Controller can execute the access requests on other Devices preferentially according to a certain scheduling algorithm to improve the overall memory access performance of the system.
NOTE: Only one of CS0 and CS1 can be enabled at the same time, that is, only one Device can be accessed at the same time.
The organization described above only increases overall capacity, not bandwidth. The organization described in the figure below can increase both overall capacity and bandwidth.
In the above figure, multiple DRAM Devices share the control bus and the Chip Select signal. The DRAM Controller accesses each DRAM Devices at the same time, and the data of each Device is merged together. For example, the data of Device 1 is output to the DATA of the data bus.[0:7] On the signal, the data of Device 2 is output to the DATA of the data bus[8:15] superior. Under such an organization, accessing 16 bits of data only requires one access cycle to complete, and does not need to be decomposed into two 8-bit access cycles.
2. Multi Channel DRAM Controller Organization
MulTI Channel means that the DRAM Controller has only multiple groups of control and data buses, and each group of buses can access DRAM Devices independently. In this scenario, the connection between DRAM Controller and DRAM Devices is as follows:
2.1 Connecting Single Channel DRAM Devices
The advantage of this organization method is that multiple Devices can work at the same time, and the DRAM Controller can initiate read and write requests to Devices on different Channels at the same time, which improves the throughput of read and write requests.
NOTE: CS0 and CS1 can be enabled at the same time, that is, at the same time, two Devices can be accessed at the same time.
2.2 Connect MulTI Channel DRAM Device
In some DRAM products, such as LPDDR3, LPDDR4, etc., the design of MulTI Channel is introduced, that is, a DRAM Devices includes multiple Channels. In this way, the effect of simultaneous access of Multi Channel can be achieved on a single Device, which will eventually lead to an increase in the throughput of read and write requests.
2. DRAM module
The full English name of DRAM is “Dynamic RAM”, which is translated into Chinese as “dynamic random access memory”. . DRAM can only hold data for a short time. In order to retain data, DRAM must be refreshed at intervals. If the memory cells are not refreshed, data is lost. DRAM is used for normal data access. We often say how big the memory is, mainly referring to the capacity of DRAM.
The basic unit of all DRAMs consists of a transistor and a capacitor. Please see the picture below:
The above figure is just a schematic diagram of the structure of a basic unit of DRAM: the state of the capacitor determines whether the logic state of the DRAM unit is 1 or 0, but the feature of the capacitor being used is also its disadvantage. A capacitor can store a certain amount of electrons or electric charge. A charged capacitor is considered a logical 1 in digital electronics, while an “empty” capacitor is a 0. Capacitors cannot maintain the stored charge for a long time, so the memory needs to be refreshed regularly to maintain the temporarily stored data. Capacitors can be charged by current – of course, this current is limited, otherwise the capacitor will break down. At the same time, the charging and discharging of the capacitor takes a certain amount of time. Although this time is very short for the capacitor in the basic unit of memory, only about 0.2-0.18 microseconds, the memory cannot perform access operations during this period.
According to some data from DRAM manufacturers, the memory needs to be refreshed at least every 64ms, which means that the memory needs to be refreshed 1% of the time. The automatic refresh of memory is not a problem for memory manufacturers, but the key is to keep the contents of the memory unchanged when the memory cell is read – so the DRAM cell must be refreshed after each read operation: perform a return operation. Write operations, because read operations also destroy the charge in the memory, which means it is destructive to the data stored in the memory. So the memory not only needs to be refreshed every 64ms, but also after every read operation. This increases the cycle of the access operation, of course, the longer the latency period. SRAM, static (Static) RAM does not have the problem of refresh, a SRAM basic unit includes 4 transistors and 2 resistors. It does not store data by using the characteristics of capacitor charging and discharging, but uses the state of the setting transistor to determine the logic state – the same as the logic state in the CPU. The read operation is not destructive to the SRAM, so the SRAM does not have the problem of refresh.
SRAM can not only run at a higher clock frequency than DRAM, but also has a much shorter latency than DRAM. SRAM takes only 2 to 3 clock cycles to load the required data from the CPU cache, while DRAM takes 3 to 9 clock cycles (here we ignore the time for the signal to travel between the CPU, chipset and memory control circuits) ).