Roadmap for High Aspect Ratio Etching and Nanoscale Patterning to Advance Memory

【Introduction】As market demand drives memory technology towards higher density, better performance, new materials, 3D stacking, high aspect ratio (HAR) etching and extreme ultraviolet (EUV) lithography, Lam Group is exploring the next three Challenges that may be faced by five-year production, provide solutions for fabs at an economical cost.

Lam Group is exploring the next three to five years as market demand drives memory technologies towards higher density, better performance, new materials, 3D stacking, high aspect ratio (HAR) etch and extreme ultraviolet (EUV) lithography Production challenges that can be faced, providing fab solutions at an economical cost.

One way to increase the storage capacity of 3D NAND flash memory is to stack additional layers, but the increase in stack height brings greater challenges. While the most obvious of these challenges is structural stability, the increased number of layers means that deeper vias are needed to reach each wordline, as well as narrower slit trenches to isolate the vias that connect to the bitlines (Figure 1). ).

Roadmap for High Aspect Ratio Etching and Nanoscale Patterning to Advance Memory

Figure 1: As 3D NAND stacks exceed 128 layers, stack heights approaching 7 microns, and transform the required via holes and slits into high aspect ratio (HAR) features, the etch challenge grows.

Challenges of High Aspect Ratio Etching

Deposition of alternating oxide and nitride thin film layers is where the 3D NAND production process begins, before hardmask deposition and openings are formed to etch the vertical channels, where the high aspect ratio etch challenge begins.

As the industry moves towards 128 layers and beyond, stack depths are approaching 7 microns, hard masks are around 2-3 microns thick, and via hole aspect ratios are approaching 90 to 100.

After this, the “ladder-like” structure shown in Figure 1 is created, before tackling the challenge of forming slits in a large number of layers. A hard mask is deposited, openings are patterned and etched in a single step to form slits in all layers. Finally, the nitride layer must be removed and the tungsten word lines created.

For reactive ion etching (RIE) of high aspect ratio structures to work, there must be a synergy between ions and neutral reactants. However, this synergy is easily lost when dealing with high aspect ratio structures, hindered by multiple mechanisms.

Roadmap for High Aspect Ratio Etching and Nanoscale Patterning to Advance Memory

Figure 2: Ions and neutral reactants are shielded. Aspect-ratio-dependent conductance and ion angular distribution are important contributors to defects such as critical dimension variation, etch incompleteness, bending, and twisting.

First, high pressure causes ions in the plasma sheath to scatter and disperse the usually anisotropic ion energy or angular distribution. As a result, the ions miss the hole or enter at a greater angle, hitting the top or sidewall of the feature. This ion “shadowing” shifts the ion-neutral reactant flux ratio away from synergy (Figure 2).

If ions are pushed down high aspect ratio features, ion energy may increase, but this increases mask consumption, which in turn requires innovations in thicker masks or hardmask materials.

In addition to this challenge, there is the problem of ions hitting the sidewalls and causing the critical dimension (CD) in some parts of the channel to be larger than desired. When this “bend” (Figure 2) becomes too large, it can cause the two holes to come together.

But there’s a bigger problem — “twisting” along the hole, which is a slight change in the ion angular distribution due to the charging effects of higher-order harmonic deformations in the RF plasma system.

Solutions to High Aspect Ratio Etch Problems

A closer look at plasma systems, especially RF subsystems, reveals a solution. It turns out that reducing the frequency so that the ion transport time accelerated through the high-voltage sheath approaches half a cycle maximizes the peak ion energy for a given RF power. The lower frequency and higher ion energy peak lead to a reduction in the angular distribution of the ions, making them more likely to reach the bottom of high aspect ratio features (Figure 3).

Roadmap for High Aspect Ratio Etching and Nanoscale Patterning to Advance Memory

Figure 3: Reducing the plasma frequency reduces the angular distribution of ions, increasing their likelihood of reaching the bottom of high aspect ratio features.

As a result, hardware designs focus on lower frequencies, higher power, and lower duty cycles.

Despite the change in hardware design, etching via holes 6.9 microns deep in common oxide/nitride (ONON) with 128 or more layers is still very difficult.

Therefore, Lam is testing a different approach to achieve the desired etch depth by first etching the via hole by setting (say 5 microns) and then depositing a protective liner on the sidewalls to avoid excessive Lateral etching. In subsequent steps, the via holes are etched all the way down to 6.9 microns.

A liner was added to perform an additional 1 micron etch without increasing the critical dimension of the overall structure. While the process still requires a lot of optimization, the test showed a promising way to etch smaller and deeper holes.

Graphical challenges and collaborative optimization

Graphics of logic and memory may be a top priority for chipmakers to cut costs and optimize performance. Now, it’s all about shrinking to a smaller structure with minimal changes. This change can be measured by Edge Positioning Error (EPE).

For example, aligning holes is challenged by several variables, such as line edge roughness, scanner registration accuracy error, and critical dimension variation, including local critical dimension variation caused by random errors in EUV exposure. Device design is often limited to extremes of variation, not averages. For example, managing these changes to accommodate worst-case scenarios can take up to 50% of the logic backend area and significantly increase manufacturing costs.

One way to control variation is through process-to-process co-optimization, which usually means compensating for lithography errors during etching. For the synergistic optimization to work, the etch equipment must have suitable tunability to better control the etch behavior across wafers as well as wafer-to-wafer.

Because wafers will always experience different plasma conditions and gas distributions, creating controlled temperature variations in turn enables process tunability and helps compensate for variations within the chamber and from the lithography machine.

One way to control the temperature and therefore the etch rate is to create adjustable temperature zones on the chuck and wafer. For over a decade, chucks have evolved from single-zone equipment in the early 2000s to dual-zone equipment, and then radial multi-zone. More recently, Lam’s Hydra® Uniformity System has evolved to non-radial multi-zone.

Simplify multiple graphics

Multi-patterning, primarily for DRAM and PCRAM, and sometimes for 3D NAND, also faces challenges with critical dimension changes. Graphical schemes increase the number of process steps, and this increase means more sources of variation.

In Self-Aligned Quadruple Patterning (SAQP), variations in lithography, deposition and etch can lead to three different critical dimensions. For example, when sidewalls are etched, the bottom layer may be dug into. This variation leads to “spacing bias”, which has become a significant challenge for multiple patterning.

This challenge can be overcome if the sidewalls can be made square after etching, which Lam has achieved through the creative use of a new metal oxide material that reduces the SAQP process from eight layers to five layers without digging deep Floor.

EUV exposes the problem of randomness

EUV lithography is expected to soon become mainstream for logic and DRAM, so the changes introduced by this process also need to be carefully considered. EUV lithography uses high-energy photons, and the process is susceptible to random variation.

For holes, random behavior results in local critical dimension changes. In the case of lines and spaces, the effects of defects such as line edge roughness (LER) and line width roughness are significant.

For example, randomness limits via yield and scales poorly with via critical dimensions. At small via critical dimensions, even 250W of scanner power may not be enough, so innovations in materials and post-processing are required to control the rising cost of EUV as power increases.

Lam’s work in atomic layer etch (ALE) over the years has demonstrated that the process can overcome this challenge. Atomic layer etching involves the self-limiting steps of surface modification followed by etching. When this cycle is repeated many times, ALE can flatten the high-frequency roughness of the feature.

Lam and its partners have measured this effect in tests, resulting in a 56% improvement in EUV via local critical dimension uniformity (LCDU) from over 3nm to 1.3nm, which may be a possibility for some chipmakers. down to 1 nanometer.

Improvements in local critical dimension uniformity have important upstream implications: EUV scanners can use lower energy due to Lam’s etch and deposition processes that reduce randomness-induced variation, and this lithography-etch technique has Co-optimization can reduce EUV costs by a factor of two.

Build the confidence to implement the roadmap

Lam has now developed module-level solutions for high aspect ratio structures as well as atomic layer processes to handle edge positioning errors in memory roadmaps. However, in order to confidently move forward along the roadmap, equipment suppliers, material suppliers and chip manufacturers must work together in the early stages of process development to meet all the requirements of the memory roadmap in a cost-effective and efficient manner.

(Source: Lam semiconductor Equipment Technology, Authors: Dr. Pan Yang, Corporate Vice President, Advanced Technology Development Division, Lam Group, Samantha Tan, Researcher, Advanced Technology Development Division/CTO Office, and Richard Wise, Vice President, Global Products Division)

The Links:   LM170E03-TLG2 NL10276BC24-21KD

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