“Market demand for higher bandwidth and higher data rates is increasing, and system frequency and modulation rate requirements are constantly increasing. Low power consumption is critical as applications once used in military and defense enter the consumer market. While meeting these requirements, there is a need to ensure that electrical performance or functionality is not sacrificed. To meet these requirements, in addition to improving signal-to-noise ratio (SNR), bit error rate (BER), and the familiar premium service, the phase noise of the local oscillator (LO) must also be improved.
By Marty Richardson, Senior Applications Engineer, Analog Devices
Market demand for higher bandwidth and higher data rates is increasing, and system frequency and modulation rate requirements are constantly increasing. Low power consumption is critical as applications once used in military and defense enter the consumer market. While meeting these requirements, there is a need to ensure that electrical performance or functionality is not sacrificed. To meet these requirements, in addition to improving signal-to-noise ratio (SNR), bit-error rate (BER), and the familiar high-quality service, the phase noise of the local oscillator (LO) must also be improved.
The new ADF5610, an integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO), is the result of ADI’s commitment to solving these problems.
The ADF5610 covers a total of 8 octaves with a VCO fundamental frequency range from 3.65 GHz to 7.3 GHz, which can be fed back to the PLL to minimize phase noise. The single-ended output (RFOUT) doubles the fundamental frequency to provide frequencies from 7.3 Ghz to 14.6 GHz, while the differential output supports 57 MHz simultaneously by using divider settings of 1/2/4/8/16/32/64/128 to 14.6 GHz full frequency range.
Figure 1. Functional block diagram of the ADF5610.
The ADF5610’s VCO architecture enables excellent wideband synthesizer performance while maintaining industry-leading phase noise performance of C114 dBc/Hz nominal open-loop phase noise at 10 GHz, 100 kHz offset. The internal state machine enables frequency settling times below 40 μs using only a passive loop filter; no additional circuitry or look-up tables (LUTs) are required unless faster settling times are required.
Excellent PLL performance for converter clocking applications
While the phase-locked loop (PLL) inside the ADF5610 has a moderate figure of merit (FOM) of C229 dBc/Hz (C232 dBc/Hz in high current mode), considering the 1/f noise (C129 dBc/Hz) and excellent VCO phase noise characteristics, rms jitter below 38 fs (1 kHz to 100 MHz integration limit) can be achieved. Therefore, the ADF5610 is ideal for demanding converter clocking applications. The loop filter resistor value should be kept to a minimum to achieve low thermal noise in the high frequency (100 MHz) range. To achieve this level of performance, an ultra-low noise voltage reference must be used.
Figure 2. RMS jitter: 8.0 GHz.
Figure 3. RMS jitter: 14.4 GHz.
Communications and Instrumentation LO
In addition to its wide frequency coverage, industry-leading phase noise, and extremely fast lock time, the ADF5610 has other features that make it ideal for wireless and instrumentation applications. In these applications, the ADF5610 is typically used as a local oscillator.
The 24-bit fractional resolution is quite good, and when used in conjunction with the precise frequency mode feature of the ADF5610, it is possible to achieve zero (0 Hz) error frequency generation. When using the ADF5610 as a local oscillator, since the nominal output power is 5 dBm, the active mixer can be driven directly through the RFOUT port, which eliminates the need for additional amplifier circuits and saves valuable board space. When used single-ended, the differential divider (PDIVOUT/NDIVOUT) has a nominal output power of 2 dBm, however, in narrowband applications, the differential can be combined with a low-loss balun or hybrid coupler to achieve 1 ~2dB increase in output power.
Low power consumption is so important these days, the ADF5610 consumes less than 700 mW in low current mode, with the output divider disabled, even in the worst case (high performance mode, output divider set to divide-by-128) , ( ) its power consumption is slightly higher than 1 W. Even in low current mode, the phase noise performance of the ADF5610 is class-leading, increasing by only 2 dBc/Hz.
The ADF5610 also has excellent spurious performance with PFD spurs as low as -105 dBc and in-band unfiltered integer boundary spurs nominally -45 dBc.
The ADF5610 PLL/VCO is available in a 7 mm × 7 mm, 48-pin land grid array (LGA) package. Very little external decoupling is required for operation, so small solutions can be used to achieve excellent performance. For best performance, a high-quality low-dropout (LDO) regulator such as the ADM7150, LT3045/LT3042, or HMC1060 is recommended. The VCO requires a 5 V supply, and the rest of the circuit is powered from the 3.3 V rail. The ADF5610 can be simulated with ADIsimPLL™ to help the user design the appropriate external component circuit required to implement a complete PLL frequency synthesizer.
With industry-leading frequency coverage, excellent phase noise performance, high output power, low power consumption and small size, the ADF5610 can meet the demanding requirements of new communications and instrumentation systems.
About the Author
Marty Richardson joined ADI in 2014 as a Senior Applications Engineer in the Microwave Frequency Generation Group. He has worked in the RF/Microwave field for over 35 years and has previously worked in design and reliability technology. Currently, he is primarily responsible for Phase Locked Loop (PLL), Voltage Controlled Oscillator (VCO) and Frequency Multiplier products. A senior member of the IEEE, he spends his free time with his family, and enjoys gardening, hunting, fishing, and mountain biking.