Lattice’s iCE40 HX ultra-low power mobileFPGA series, compared with any other CPLD or FPGA devices, can provide the lowest static and dynamic power consumption, about 640 to 7680 logic units and flip-flops, each device contains 8 to 32 RAM blocks, each block has 4Kb storage for data storage and buffering, especially suitable for cost-sensitive and large-volume applications. This article introduces the main characteristics of the iCE40 HX series, the architecture diagram of the iCE40 HX series, the main products and Features, as well as the main features of the iCEblink40 iCE40HX1K evaluation board, circuit diagram, main component list and PCB component layout diagram.
The Lattice semiconductor iCE40 LP-Series and HX-Series programmable logic family are designed to deliver the lowest static and dynamic power consumption of any comparable CPLD or FPGA device. iCE40 FPGAs are designed specifically for cost-sensitive, high-volume applications. iCE40 FPGA are fully user-programmable and can self-configure from a configuration image stored in on-chip, nonvolatile configuration memory (NVCM) or stored in an external commodity SPI serial Flash PROM or downloaded from an external processor over an SPI-like serial port. iCE40 components deliver from approximately 640 to 7,680 logic cells and flip-flops while consuming a fraction of the power of comparable programmable logic devices. Each iCE40 device includes 8 to 32 RAM blocks, each with 4Kbits storage, for on-chip data storage and data buffering.
Each iCE40 device consists of five primary architectural elements.
An array of Programmable Logic Blocks (PLBs)
Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of…
A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of up to four inputs, regardless of complexity
A’D’-type flip-flop with an optional clock-enable and set/reset control
Fast carry logic accelerates arithmetic functions: adders, subtracters, comparators, and counters.
Common clock input with polarity control, clock-enable input, and optional set/reset control input to the PLB is shared among all eight Logic Cells
Two-port, 4Kbit RAM blocks (RAM4K)
256×16 default configuration; selectable data width using programmable logic resources
Simultaneous read and write access; ideal for FIFO memory and data buffering applications
RAM contents pre-loadable during configuration
Four I/O banks with independent supply voltage, multiple Programmable Input/Output (PIO) blocks
LVCMOS I/O standards and LVDS outputs supported in all banks
I/O Bank 3 supports additional LVDS, and SubLVDS I/O standards
One or two Phase-Locked Loops (PLL)
Very low power
Clock multiplication and division
Phase shifting in fixed 90° increments
Static or dynamic phase shifting
Programmable interconnections between all programmable logic functions
Eight dedicated low-skew, high-fanout clock distribution networks
Main features of iCE40 HX series:
Figure 1. Architecture and features of iCE40 HX series
The main products and features of the iCE40 HX ultra-low power programmable logic series:
The HX-Series of the iCE40™ “Los Angeles” mobileFPGA™ family is ideal for tablet applications.
Designers of handheld, battery-based consumer products have long awaited a programmable logic solution that delivers design flexibility and fast time-to-market benefits coupled with features that address their power, logic capacity, cost, and small form factor requirements. This solution, previously unattainable by other FPGA suppliers, is now provided by Lattice’s ultra-low power mobileFPGA devices.
Utilizing the mobileFPGA platform, mobile designers can quickly bring new features and custom functionality to market with their very own Custom Mobile Device. Designers can achieve this by either using state of the art development software or by utilizing Lattice’s design services.
Ideal for sensor management functions including interrupt filtering, interrupt aggregation, auto polling
Battery insertion and audio insertion detection with high speed comparators
Support MIPI SLIMbus Interface
High speed LVDS channels up to 525 Mbps per channel
High definition video support: HD720p @ 60Hz, HD1080p @ 30Hz
Supports MIPI DBI and MIPI DPI video interface standards
High Speed USB 2.0 host and device controllers supporting ULPI and UTMI interfaces Ideal for 3D solutions
PCB friendly footprint packages
Fabricated on advanced 40nm standard CMOS process
50% faster than iCE65™ devices
Ultra-low power consumption
Ultra-small footprint packages
World’s first 2.5 x 2.5 mm, 0.4mm pitch ball grid array
2X logic capacity per mm2 over iCE65
Up to 2 phase-locked loops supporting dual outputs
Flexible block RAM
iCEblink40 iCE40HX1K Evaluation Board
This guide describes how to begin using the iCEblink40 Evaluation Kit, an easy-to-use platform for rapidly prototyp-ing designs using the iCE40 mobileFPGA™.
Main features of iCEblink40 iCE40HX1K evaluation board:
• High-performance, low-power iCE40HX1K mobileFPGA
• USB programming, debugging, virtual I/O functions, and power supply
• Four user LEDs
• Four capacitive-touch buttons
• 3.3 MHz clock source
• 1Mbit SPI serial configuration PROM
• Supported by Lattice iCEcube2™ design software
• 68 LVCMOS/LVTTL (3.3V) digital I/O connections on 0.1” through-hole connections
• Supports third-party I/O expansion boards and modules, including 3.3V Arduino Shield boards (requires additional sockets, not supplied)
Figure 2. Outline drawing of iCEblink40 iCE40HX1K evaluation board
Figure 3. Component layout and board size of iCEblink40 HX1K evaluation board
Figure 4. Circuit diagram of iCEblink40 iCE40HX1K evaluation board
The main material list of iCEblink40 iCE40HX1K evaluation board:
For details, see: