“LED technology is more and more applied to our lives. For developers, it is necessary for developers to realize LED or other equipment sequencers through a system on chip (SOC) platform, so as to find a design requirement that reduces costs and reduces design difficulties. More and more common. The SOC device integrates the single chip microcomputer functions and various digital peripherals required by the complete LED subsystem through a single chip.
LED technology is more and more applied to our lives. For developers, it is necessary for developers to realize LED or other equipment sequencers through a system on chip (SOC) platform, so as to find a design requirement that reduces costs and reduces design difficulties. More and more common. The SOC device integrates the single chip microcomputer functions and various digital peripherals required by the complete LED subsystem through a single chip. This article introduces a simple 8 LED light sequence based on the new SOC technology. The wonderful part of this design is that no intervention is required. Instead of using traditional passive digital peripherals intervened by a single-chip processor, this design is entirely based on the intelligent distributed processing function of the SOC digital system. This frees the central processing unit from the work of managing the light sequence circuit, saves CPU resources and makes the design more efficient.
This design method can be easily extended to other devices other than LEDs that need to be turned on or off in a specified order, such as sequence timers of different lengths and different modes, and so on. There are additional features in this design example:
7-digit counter (TC) terminal count
Instruct the device to turn on and off the output
8-bit output for serial devices
Clock input to the Verilog state machine
Bus clock for 8-bit ALU (bit-slice) processor
What is used in this article is the integrated development environment PSoC Creator of Cypress semiconductor‘s programmable system-on-chip (PSoC).
The design step is to create a Verilog symbol to define the input, output and bit widths associated with it (see Figure 1). Once the upper Verilog model (schematic diagram) has been established, it can be used to generate a Verilog source file containing the pin definitions of all modules. This step does not require the development of functional Verilog code.
Figure 1: Verilog symbol.
The Verilog symbol just created can now be placed in the high-level schematic design. Here, every input and output can be connected to clock sources, I/O pins, status and control registers, etc. The high-level principle design of 8-LED lamp sequence circuit is shown in Figure 2.
Figure 2: Example of high-level principle design.
So far, Verilog symbols have been created, placed in the high-level principle design, and connected to the I/O and clock of the device. It is now possible to generate Verilog code to perform certain functions, in which the LEDs can be flashed. In order to manage the logical capabilities of the sequence, a simple data path can be introduced into the design.
This data path includes an 8-bit ALU with a simplified instruction set, two data registers, two accumulators, shift and comparison logic, and a 4-deep 8-bit FIFO. In order to keep the design simple, only two ALUs are used to set the accumulator to 0, and the accumulator is incremented every time the sequence is turned on or off. For more complex sequencing designs, developers can combine multiple ALUs to form a 16-bit or 24-bit processor. Such a processor is similar to the bit-slice processor, which was more popular in the 70s and early 80s, and it can provide sufficient processing power for sequential subsystems.
The data path configuration tool is shown below. Please note that the first two lines of CFGRAM (configuration RAM) comment: “A0